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Verifying Virtual Prototypes Key to IOT Success

Yatin Trivedi, DVCon Chair, talks about Internet-of-Things verification issues and differences between standard specifications and implementations efforts.

By John Blyler, Editorial Director

As the general chair of the upcoming semiconductor chip design and verification conference (DVCon), Yatin Trivedi discusses the challenges in verifying Internet-of-Things (IoT) system-level designs plus the way that Accellera and the IEEE partner on standards. What follows is a portion of that interview. – JB

Blyler: Has the rise of the Internet-of-Things (IoT) technology affected the type of topics at DVCon?

Trivedi: IOT as a technology is probably not showing up at DVCon directly. But indirectly more and more designers need to quickly verify sensor systems and new applications. So dealing with sensors and sensor based verification methodology is something that people are addressing.

Engineers are also looking at virtual prototyping the entire IoT system. Consider a wearable device that monitors your blood pressure. The interesting thing is not just the device but simulating the system that provides all the data and pushes it to the cloud for analysis. A carefully constructed virtual system will allow you to study all the data bandwidth, privacy and security issues. People need to build these virtual systems as quickly as possible and those are some of the topics people discuss at DVCon.

Blyler: The challenge seems to lie beyond the design of the individual end node. Is that right?

Trivedi: Yes – The challenge lies in visualizing the flow of data and information from the sensor to the cloud and partitioning analysis at each location. How do all the sensors in an IoT network provide data and then how can that processed information feed back into the system to react in an appropriate way? Answering these challenges is the task of a virtual prototype.

These issues are particularly important to our DVCon communities in the US and Europe with their large presence in the automotive space. They have research departments working to create mixed signal simulations to quickly prototype such systems.

Blyler: A few years ago, I talked with Dennis Brophy, past Accellera Chair, about the organization’s growing interest in the software development side of hardware-software integration and verification. Are these topics falling within the interest of DVCon?

Trivedi: Hardware and software integration challenges are taking shape under Accellera. But they haven’t made their way into the DVCon program yet. Still, differences between standards and implementation strategies are being reflected at DVCon. For example, the Universal Verification Methodology (UVM) is both a documented standard specification and a proof of concept library.

In fact, the way the Accellera committee works with the IEEE is a classic example of this differentiation. You may recall that Accellera originally developed two things simultaneously; the UVM standard specification and the UVM base class library for implementation. Accellera contributed the standard to the IEEE. It is now known as the IEEE 1800.2 project, which is really a System Verilog based UVM – that is, UVM written in and for System Verilog. [Editor’s Note: UVM 1.2 builds on the IEEE 1800™ SystemVerilog standard by specifying an application programming interface that defines a base class library using the SystemVerilog language constructs.]

Blyler: I imagine that the implementation part is more dynamic than the specification part.

Trivedi: Yes – People who are using the reference library implementations are finding issues. Thus the implementation libraries are revised as the bugs and other issues are resolved. As long as the implementation details change, but the interface doesn’t, then the standard itself doesn’t need to change. It is a common software class library situation. As long as the class definition doesn’t change, the class implementation can continue to evolve and become more accurate, better preforming and use less memory. As long as the class definition remains the same, then the object behavior is well defined.

That separation of specification documents and implementation is the new way that Accellera is working with the IEEE. The IEEE continues to focus on the standard while Accellera continues to support the implementation in an open source forum. Shishpal Rawat, Accellera Systems Initiative Chair, can provide you with more details on the separation between the standard as a document and the standard as an implementation.

Blyler: Is there one major trend that will be highlighted at DVCon this year?

Trivedi: It seems as if there has been one common theme over the years, namely, how verification problems have gotten worse but the tools have become smarter. So on balance things are the same. (laugh) In the past, we were developing 10,000 gate designs using tools that were primitive by today’s standards. It represented a degree of difficulty that could be measured as a ratio of complexity. Today the problem has become larger and those tools have become smarter and more numerous – from simulators and emulators to virtual prototyping tools. So the overall complexity ratio appears to have remained the same.

Blyler: Anything else?

Trivedi: I’d like to express my thanks to all of the steering and program committee members and other volunteers who do so much work! Over the last 7 to 8 months, these people have really brought things together for DVCon. I cannot thank them enough.

Blyler: Having worked on such activities in the past, I can say that recognition is always appreciated.

Originally posted on Chipestimate.com IP-Insider

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