Tag Archives: UVM

Yatin Trivedi, DVCon Chair, talks about Internet-of-Things verification issues and differences between standard specifications and implementations efforts.

High-level synthesis in design and verification, layering UVM constraints, FORTRAN? still?, parallel algorithms, two new (and free!) VIPs from AMIQ; the NVMe SSD standard; and Apple batteries and the IoT

The often-misunderstood UVM factory object provides a path to modify testcase behavior without the associated doom of touching already released code. by Hamilton Carter, Senior Editor All of us have seen some variation of the following flow chart:   The basic message, “If you can get away without touching it, you might just be OK,” applies as well to design verification …

UVM platform specifics and coding examples; ringing MOSFETs; the capture, care, and upkeep of young engineers; post-DVCon coverage, and building vs. Jaguar

Engineering Resolutions; Vehicle Comm.; Chip-Level Security; UVM; Data Man. Report; Verifying Si; VCOs, Low-Power DDR4; IoT Regulations; Transformers.

A look at the IoT and new, near-field comm technology; the TechMuseum of Innovation Applied Materials Tech Awards; applying the IoT to things that build the IoT, (does that make it a self-aware IoT?); and a few language structure pieces for the hardcore coder in each of us.