Home » IP Systems » IP Systems Blog Review – Tuesday April 28, 2015

IP Systems Blog Review – Tuesday April 28, 2015

Big data and verification; reading design specs; all-digital radio; protocols: WiGig and HART; more from the Wilson verification study: FPGAs; the Studebaker plant gets a new lease on life; verification sequence portability; NASA space apps; draw a barn with SystemVerilog constraints; Industrial automation and the IoT; and upcoming events

by Hamilton Carter – Senior Editor

AMIQ wrote up a great beginner’s guide to reading design specifications.  It briefly details not only what to look for, but what to do with it once you’ve found it.

Cadence’s Steve Brown introduces the WiGig standard.  Wireless displays anyone?

Researchers at Cambridge Consultants have demonstrated the first all-digital radio transmitter.

Analog Devices discusses the highway addressable remote transducer (HART) protocol for frequency shift keying digital communication.  Learn about the protocol as well as how to design filters for it.

Mentor’s Harry Foster continues to walk us through the Wilson Research Group Functional Verification Study.  Part IV covers FPGA Verification Effectiveness.

Studebaker plant to become high-tech office and living space:  South Bend entrepreneur Kevin Smith is renovating the space.  It’s his newest venture modeled after his move of his company—Deluxe Sheet Metal—into South Bend’s deserted train station.

Here’s a very nice paper demonstrating UVM-ML enabled reuse of sequences in a mixed SystemVerilog/e environment[pdf].  It’s by Hannes Fröhlich and Kishore Sur of Cadence Design Systems and was published at DVCon India 2014.  Apparently it was also a poster[pdf].

NASA hosted a space apps challenge in 133 cities around the world on April 10 – 11.  Find out about the apps—including an autonomous spacecraft docking/tracking camera—that were developed at the San Francisco hackathon.

Mentor’s Warren Kurisus discusses upcoming challenges and changes in industrial automation and the industrial IoT.

The Verification Gentleman solves the “Draw the Barn” problem using SystemVerilog constraints.  The problem presents a fun way to learn more about SV data structures and constraints.

barn_thumb

Dean Drako of IC Manage discusses the use of ‘big data’ in chip design projects.  Among promising target areas are ‘Verification Suite Coverage’ and ‘Analyze Regressions’.  Get ready!

Upcoming Events:
Intorducing a new feature to the weekly blog review, a listing of upcoming conferences.  If you know of one that should be added, please let me know!

 

Event Location Dates
IoT DevCon Santa Clara, CA May 6 – 7
International Microwave Symposium Phoenix, AZ May 17 – 22
Freescale Technical Forum Austin, TX June 22 – 25

Great information delivered straight to your inbox

Leave a Reply

Your email address will not be published. Required fields are marked *

*