Tag Archives: SystemVerilog

Big data and verification; reading design specs; all-digital radio; protocols: WiGig and HART; more from the Wilson verification study: FPGAs; the Studebaker plant gets a new lease on life; verification sequence portability; NASA space apps; draw a barn with SystemVerilog constraints; Industrial automation and the IoT; and upcoming events

Blog Review 12/24/2014 by Hamilton Carter Technology Editor   Mentor’s Robin Bornoff begins a multi-part series on energy conservation through the responsible stewardship of hot water.   Catherine Bolgar covers recent predictions that the next industrial revolution will be spurred by doing more with fewer material resources.   Intel has added new cache monitoring technology to their Xenon class processors.  …