Tag Archives: Silicon Labs

The benchmarking organization seeks to create performance tests for the edge of the Internet of Things (IoT). By Chris Edwards, Tech Design Forum Benchmarking organization EEMBC has kicked off an effort to develop a set of performance tests for edge nodes for the Internet of Things (IoT). Focus on the energy efficiency of edge nodes, the benchmarks will build on …

High-level synthesis in design and verification, layering UVM constraints, FORTRAN? still?, parallel algorithms, two new (and free!) VIPs from AMIQ; the NVMe SSD standard; and Apple batteries and the IoT

Xilinx in space; lenssless optics; the AMBA coherent host interface; the downside of silos; vertical companies; gender inequity; PCIe Gen 4; and the de-evolution of the SoC

This year’s Embedded World saw chip makers rising to the challenges presented by new IoT applications.

The digital isolator circuit has gone CMOS. Integrated designs circumvent the capacitative bandwidth limitations and other issues of the venerable old opto-isolator.

Buffer, and ADC design considerations; all about timing specifications; portable stimulus; Star Trek and the IoT; the Wilson Group's functional verification study; RTOS performance; the Silicon Valley age gap; temperature and humidity sensors; requirements management; and the oft-dreaded question "What do you do for a living?"

Hot IoT Stats, Data Privacy, MediaTek Goes Mobile, Not-so Intimate Details, IT Affected, Maker Faire Contest, Bluetooth Battle, Intelsat/Kymeta, Energy Solutions

Experts from Synopsys, Imagination Technologies, and Silicon Labs expand on what they saw at CES 2015 and what it means for hardware and software IP subsystem designers. by Hamilton Carter, Senior Editor The shorter market windows associated with burgeoning IoT and entertainment product offerings are creating new challenges for hardware and software IP designers alike.  We spoke with Eric Huang, …

Android assembly programming, Sample and Hold Time for Dummies, near field communications, and the secret origin of the Udacity functional verification course By Hamilton Carter, Senior Editor The Altera SoC FPGA was selected for Audi’s advanced driver assistance system, (ADAS). How to program in assembly on an ARM/Android device. Mentor’s Josh Rensch provides quirky, irreverent advice on how design and …