Tag Archives: Cadence

EDA Tool Reduces Chip Test Time With Same Die Size

Cadence combines physically-aware scan logic with elastic decompression in new test solution. What does that really mean? By John Blyler, Editorial Director Cadence recently announced the Modus Test Solution suite that the company claims will enable up to 3X reduction in test time and up to 2.6X reduction in compression logic wirelength. This improvement is made possible, in part, by …

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IP Systems Blog Review – Sunday May 10, 2015

Debugging the debug process; homing in on UPF; sound digitization schemes; unit testing assertions; occupant aware homes; embedded system-level verification; the unexpected consequences of uninitialized variables; and glow-in-the-dark DDR4.

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IP Systems Blog Review – Tuesday April 28, 2015

Big data and verification; reading design specs; all-digital radio; protocols: WiGig and HART; more from the Wilson verification study: FPGAs; the Studebaker plant gets a new lease on life; verification sequence portability; NASA space apps; draw a barn with SystemVerilog constraints; Industrial automation and the IoT; and upcoming events

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