EDA Inflections on Technology Innovations

Each of the major semiconductor EDA companies approaches innovation is different ways, but
all agree that creating new products and improving existing ones is essential to survival.
By John Blyler
Everyone talks about innovation. Start-up companies are the most visible vehicle for innovation, but also the most risky with a one-in-ten chance of modest success. Less visible is the innovation that constantly must occur in fully formed, large companies if they are to continue to succeed. System-Level Design (SLD) talked with the three major EDA companies about the challenges to innovation: Michael McNamara, Vice President and General Manager of System Level Design at Cadence; Serge Leef VP, New Ventures GM, System-Level Engineering Division;Michael Jackson, VP of Engineering, Physical Design, Synopsys, Inc.
SLD: How do you foster innovation inside an existing, successful company? How do you create new products inside a large and often bureaucratic commercial organization?
McNamara: A good example was the C-to-Silicon product line, a high-level synthesis tool. This product started inside of Cadence labs back I 1998, originating from a project called Metropolis with UC Berkeley. This project focused on the system-level development space and was the genesis of platform-based design. The idea was that you would have a single platform that you then customize for different usages. A modern example is today’s Droid phones that use TI’s OMAP to incorporate an ARM process, graphics, Bluetooth and other radios into a collection of IP that is aggregated together. Other’s than start with this platform to add their unique innovation and wham, in 6 months you have a cell phone.
In 2002, an internal design team was exploring the idea of high-level synthesis. The idea was that a C-code program running a microprocessor could serve as a specification for what would need to be done by the hardware device. In those days, we had a silicon compiler but needed to create a register-transfer-level (RTL) language as an in-between language. It was too hard to go all the way from C to transistors.
Interestingly enough, there was a product in the late 90’s called Behavioral Compiler, but it turned out to be a failure. The promise of high-level synthesis was huge, but it just wasn’t happening.  Finding out why was the first goal of our research task and is a key difference between research and implementation (or product) groups. Research labs can step back and examine why things aren’t working as expected. We started by interviewing some two dozen companies who were doing various levels of high-level synthesis.
Our internal R&D group asked them why wasn’t high-level synthesis working? Those interviews identified a couple of issues. One was a manufacturing challenge correcting design issues, i.e., if RTL is automatically generated, how do accommodate changes such as specification or place and route changes?
[Sidebar: “One of the problems with high-level synthesis is dealing with ECO – Engineering Change Option/Order. High-level synthesis involves developing C-code. But if you are not writing the lower-level RTL-Code, then how do you know which bit of RTL needs to be changed to address manufacturing issue or even a late specification change in the C code. How can you implement a late change in the C code that doesn’t change every single line of the RTL? It’s not uncommon for such changes to delay the completion Place and Route (P&R) layout by several weeks.” – MacNamara
Another issue identified by the R&D group was the challenge of reuse. Designers really want a way to specify how the C-code program would be implemented in any given design. One example is the use of decoding and compression algorithms for video movies for different end user applications, from smart phones to laptop computer to large home entertainment theater systems. You are using the same exact algorithms, the each implementation requires a different set of power, performance and quality requirements. Quality issues might be that the smaller screen sizes on a smart phone don’t need the same display resolution as a home theater.
That was the nature of the research part of this project. The researchers gather a bunch of data, then formulated three or four ideas that they believe constituted the major roadblocks for the adoption of this technology. Around this same time, Cadence had serendipitously purchased a high-level synthesis tool from a company called Get-to_Chip. Suddenly, the researchers at Berkeley labs had a a high-level synthesis tool that they could play with and try to implement some of their ideas to address the technology roadblocks, like ECO implementation and the separation of constraints from design.
The Get-to-Chip tool read and generated Verilog, but it didn’t support C or C++ or SystemC. But the researchers could use this tool to develop a prototype. The first step was involved research to identify and opportunity. The second step involved building a prototype.
SLD: Are there other ways in which large companies try to innovate new ideas?
Leef: I basically have a non-traditional venture portfolio where I attempt to identify opportunities in markets or application domains that are adjacent to Mentor’s products, technologies or know-how. In other words, I’m looking for adjacent places where our current assets can be leveraged.  There are basically four operational models that we recognize, which I’ll list from least to the most expensive.
Adaption is the least expensive is adaptation because it augments existing horizontal product with domain specific libraries, design examples and application notes to create a vertical product.  One example would be SystemVision, a horizontal megatronic simulator, that is augmented with models applicable to implantable medical devices.
The next least expensive approach is to repurpose a relevant in-house technology and retarget it to a different domain. For us, an example of an in-house technology would be algorithm creation and implementation. We have a good understanding of optimization techniques in the EDA space. We are retargeting this technology to a different, but adjacent domain in the automotive electronic simulation market.
Let me explain. There is an elaborate cost function in vehicle distributed computing that lends well to EDA Place and Route (P&F) optimization technology. Such technology would be useful but as yet not fully applied to automotive designer.
A third way approach to adjacent markets is called incorporation. Here, we identify useful third party technology companies that can be plugged into one of our existing products. Of course, such plug-ins would need to drastically improve or alter the opportunity side for whatever it is that we have. For example, consider the development of virtual prototoypes which typically include models of microprocessors, microcontrollers and DSP cores. It is quite an expensive to develop these models organically. Let’s just say, for kicks, that there is an third party supplier of inexpensive, fast instruction set simulators. We might acquire a license to such a technology, then snap it into multiple simulation technology environments within our products. We would incorporate that technology as opposed to a stand-alone business acquisition.
The last and most expensive approach would be development.  In this situation, we have some unique know how but that is it.  In those cases, we’d invest in R&D to create something new based purely on our understanding of the problem and requisite technologies needed to solve it.
SLD: Would Calibre be an example of an R&D project?
Leef: Calibre is exactly such a case. But Calibre didn’t come through any kind of structured venture portfolio management. Instead, Calibre was truly a Skunkworks exercise, where a bunch of people worked on their own time for long periods without management noticing what they were doing. So they succeeded against organizational forces rather then because some infrastructure was in place to support the development.
What I am trying to do is create an environment where things like Calibre can grow and be nurtured in a repeatable way, as opposed to spontaneous, as what happened with the actual Calibre.
Overall, we trend to view our innovation effects in the same way as venture capitalists (VCs). Currently, I have projects that are in the A, B, C and D stages of funding and development – similar to series funding in the VC world (see Figure 1). Basically, we have a Pre-A stage, in which we explore concept to decide if business plan is warranted. In Stage A, a specific market and product are identified and we develop a prototype. Stage B consists of creating commercial strength product and engaging with early customers. Stage C is where we deploy the product to broad set of customers and hopefully generate revenue.
 

Figure 1: Here is a typical overview of the milestones faced by most startup companies in the high-technology marketplace.
SLD:  How is R&D funded within a large company?
Jackson: We fund new technology and product development in our business units as opposed to an independent R&D organization. We have had many successful innovations doing this, some recent examples include the creation of a new router (Zroute), new test compression (DFTMax), new RTL exploration (DC Explorer) and a new constraint analyzer (Galaxy Constraint Analyzer).
SLD: Do you favor internal development or acquisition as a way to innovate technology?
Jackson:  Generally, we rely more on home-grown development. This is especially true in areas where we are creating a replacement product or extending a product to address an adjacent area. Home-grown development is also used for new product areas but acquisition can also play a role here.
 
Originally published by the author in Chip Design magazine.