JB Systems Media and Tech Covering the High-Tech Semi-Electronics-Systems Industries
Mentor Graphics answers failure mode questions and simulation-testing for IGBT and MOSFET power electronics in electronic, hybrid-electronic vehicles (EV/HEV).
Read More »Tag Archives: test
EDA Tool Reduces Chip Test Time With Same Die Size
Cadence combines physically-aware scan logic with elastic decompression in new test solution. What does that really mean? By John Blyler, Editorial Director Cadence recently announced the Modus Test Solution suite that the company claims will enable up to 3X reduction in test time and up to 2.6X reduction in compression logic wirelength. This improvement is made possible, in part, by …
Read More »