Tag Archives: chip

Cadence combines physically-aware scan logic with elastic decompression in new test solution. What does that really mean? By John Blyler, Editorial Director Cadence recently announced the Modus Test Solution suite that the company claims will enable up to 3X reduction in test time and up to 2.6X reduction in compression logic wirelength. This improvement is made possible, in part, by …

Achieving the lowest digital and analog system power on a single IoT chip requires re-architecting and optimization.

John Blyler interviews Dr. Gary Ray about reproducible research in open source hardware design and impact to EDA-IP chip development.