Tag Archives: Altera

High-level synthesis in design and verification, layering UVM constraints, FORTRAN? still?, parallel algorithms, two new (and free!) VIPs from AMIQ; the NVMe SSD standard; and Apple batteries and the IoT

The holidays aren’t over yet!  Mentor’s Boris Marovic considers the science behind Santa.  Alien technology abounds. Follow an ex-Sparkfun engineer in his travels across Africa spreading robotics. Jama moved into a new headquarters for the new year! Things are a bit slow what with all the mandatory holiday shutdowns.  Here’s some fun holiday reading about the Blocks for the Intel …

by Hamilton Carter Senior Editor Altera’s Ron Wilson lays out the consequences and opportunities of what he calls the flash revolution.  Find out what stackable flash memory cells portend for your industry.   Amiq’s Stefan Birdman reports on the inaugural DVCon Europe.  Get a Birds-Eye View of Stefan’s experience there and the cool things he found.   Mentor’s Colin Walls …

by Hamilton Carter, Senior Editor   The first post-acquisition Jasper User Group (JUG) conference was heldlast Monday and Tuesday in Santa Clara California.  Cadence’s Executive Vice President of the System and Verification Group, Charlie Huang, and Jasper’s Oz Levia each spoke about how the new Jasper products fit into the Cadence system verification flow.     Ron Wilson, of Altera discusses …

A look at the IoT and new, near-field comm technology; the TechMuseum of Innovation Applied Materials Tech Awards; applying the IoT to things that build the IoT, (does that make it a self-aware IoT?); and a few language structure pieces for the hardcore coder in each of us.