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Microcontrollers and the 68000; Neural networks; Stacked dies; a Study of Studies; Always On; Smart Cities; Code Monkeys; Test Strategy; and Biometric Security

Experts from Synopsys, Imagination Technologies, and Silicon Labs expand on what they saw at CES 2015 and what it means for hardware and software IP subsystem designers. by Hamilton Carter, Senior Editor The shorter market windows associated with burgeoning IoT and entertainment product offerings are creating new challenges for hardware and software IP designers alike.  We spoke with Eric Huang, …

Android assembly programming, Sample and Hold Time for Dummies, near field communications, and the secret origin of the Udacity functional verification course By Hamilton Carter, Senior Editor The Altera SoC FPGA was selected for Audi’s advanced driver assistance system, (ADAS). How to program in assembly on an ARM/Android device. Mentor’s Josh Rensch provides quirky, irreverent advice on how design and …

Engineering Resolutions; Vehicle Comm.; Chip-Level Security; UVM; Data Man. Report; Verifying Si; VCOs, Low-Power DDR4; IoT Regulations; Transformers.

The holidays aren’t over yet!  Mentor’s Boris Marovic considers the science behind Santa.  Alien technology abounds. Follow an ex-Sparkfun engineer in his travels across Africa spreading robotics. Jama moved into a new headquarters for the new year! Things are a bit slow what with all the mandatory holiday shutdowns.  Here’s some fun holiday reading about the Blocks for the Intel …

Kickstarter Projects, Code Coverage, Specman, IP Verification, MOOC, Automotive, Mixed Signal, Conflict Free and IGBT.

by Hamilton Carter, Senior Editor   The first post-acquisition Jasper User Group (JUG) conference was heldlast Monday and Tuesday in Santa Clara California.  Cadence’s Executive Vice President of the System and Verification Group, Charlie Huang, and Jasper’s Oz Levia each spoke about how the new Jasper products fit into the Cadence system verification flow.     Ron Wilson, of Altera discusses …