Featured Stories

Yatin Trivedi, DVCon Chair, talks about Internet-of-Things verification issues and differences between standard specifications and implementations efforts.

Start-up SCiO prototypes a pocket-sized molecular scanner based on spectral imaging that tells you everything about your food.

Cadence combines physically-aware scan logic with elastic decompression in new test solution. What does that really mean? By John Blyler, Editorial Director Cadence recently announced the Modus Test Solution suite that the company claims will enable up to 3X reduction in test time and up to 2.6X reduction in compression logic wirelength. This improvement is made possible, in part, by …

A common coding practice can lead to product efficiency but also software maintenance nightmares and technical debt.

Criticalblue’s CEO David Stewart reveals how software driven hardware performance optimization moved them beyond the chip design world.

Software running close to the silicon hardware still presents many challenges for designs in terms of memory footprint optimization and security vulnerability.

Come hear semiconductor technical and business discussions from the experts at the SEMI Pacific Northwest Breakfast Forum - "The Future of Moore’s Law."

Small, low power radars use Doppler and powerful analysis to monitor heartbeats, detect home entry and reconstruct audio signal from vocal cords.

IEEE IMS 2015 celebrates Maxwell’s fundamental equations for electro-magnetic phenomenon that were almost lost to the world.

The often-misunderstood UVM factory object provides a path to modify testcase behavior without the associated doom of touching already released code. by Hamilton Carter, Senior Editor All of us have seen some variation of the following flow chart:   The basic message, “If you can get away without touching it, you might just be OK,” applies as well to design verification …