Monthly Archives: February 2016

EDA Tool Reduces Chip Test Time With Same Die Size

Cadence combines physically-aware scan logic with elastic decompression in new test solution. What does that really mean? By John Blyler, Editorial Director Cadence recently announced the Modus Test Solution suite that the company claims will enable up to 3X reduction in test time and up to 2.6X reduction in compression logic wirelength. This improvement is made possible, in part, by …

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Augmenting System Change

Design experts from many domains have a new way to collaborate change that doesn’t affect their tool flow or development process. By John Blyler, Founding Advisor And Affiliate Professor, Systems Engineering Department, Portland State University The one constant in the design of complex systems has been the necessity to communicate and manage change. Since the earliest days of modern systems …

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