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Trends Driving IP Reuse Through 2020

Semico Research’s Jim Feldhan shared detailed hardware-software intellectual property (IP) reuse trends through 2020 for the semiconductor chip market.

By John Blyler, Editor-in-Chief, “Semi-IP Systems”

Key Takeaways:

> First Time Design Starts are slowing due to complexity and cost.

> Software costs continue to outpace hardware costs.

> Reuse comprises more than 60% of design starts.

> By 2020, SOCs will be almost 130 times more complex than in 2002.

> Systems beat out processor and memory IP growth.

> Cryptography and security are among the fastest growing IP reuse blocks.

> M&A may or may not affect reuse growth.

Integrated, system-on-chip (SOC) designs form the cornerstone for almost every electronic-based product market. But without the growth of intellectual property (IP) reuse, SOC designs would be mired in overwhelming complexity and cost.  IP reuse issues were a primary topic at REUSE 2016. Jim Feldhan, CEO of Semico Research, shared his data and perspectives on the trends in reuse in the SOC market. What follows is a synopsis of his presentation. — JB

Semico divides SOCs into 3 categories: Performance, Value and Basic SOCs. Figure 1 represents the total design starts over the last few years and forecasted into the future. For example, there were about 11,000 designs by the end of 2016 with a forecasted growth to 13,300 by 2020. Over the next 5 years, the fastest growing category will be for Basic SOCs at almost 16%.

Figure 1: Design starts for three categories of SOCs.

The majority of these designs are occurring in the consumer and industrial markets. While the industrial markets typically have an easier to prove return-on-investments (ROI), the consumer market has a wider range of products. But both categories tend to have a lot of SOC designs with an overall unit growth for SOCs at about 8% over the next 5 years.

Nex, Feldhan examined the overall SOC market more closely by considering first time designs over roughly the last 20 years (Figure 2).  There was a big spike in first time design starts after the Dot-Com bubble in 2000 as companies reinvested in new architectures. Subsequently, the financial collapse in 2008 resulted in design starts falling into the negative category. Recoveries occurred over time but have slowed to low single digit growth rates. In 2016, Feldhan predicted first time designs to be around 4, 400 designs. By 2020, designs should reach about 4,900 or just under 5,000.

Figure 2: First time design starts.

Of that 5,000 design starts, most of the growth is coming from the Value and Basic SOCs, explained Feldhan. A major driver for this growth is for technology in the Internet-of-Things (IOT) market. Interestingly, we predict about 300 additional Value SOC design starts to occur between 2016 and 2020. Basic SOC should add over 600 starts during this same period while Performance SOCs will remain fairly flat in terms of growth.

Why are first-time designs for Performance SOCs so flat – hovering around 1,700? The answer comes from the rising cost of both silicon and software (see Figure 3). Both the blue and green horizontal bars attest to the increase in actual silicon hardware cost and embedded software cast for new design node, respectively. These costs were not really an issue for vendors until 90nm, when software became much more expensive. By the 40nm node, software was almost as expensive as the hardware to design.

The red bar in Figure 3 represents the cost of either the blue (hardware) or green (software) bar that is required to integrate either the hardware of the software into the SOC.  For example, at 14nm, the integration expense for a Performance SOC would be $105M for the hardware portion of the design. Of that amount, $40M would be need to integrate the IP into the actual hardware. But you will also end up spending $120M for embedded software. And it will cost $50M of that $120M to integrate the embedded software into that chip design. All of this makes the SOC very expensive.

On the business side, the escalating cost makes is a risky proposition for companies to invest in new design starts for Performance SOCs. That is one reason for the slow growth rate for these categories of chips.

Figure 3: Silicon hardware and embedded software costs rise with each manufacturing process node.

IP Reuse

How do designers deal with the rising cost of designs and complexity while achieving reduced time-to-market (TTM)? The latter has been an issue in the semiconductor industry for many decades. It has become more critical as we move into the mobile communication market as well as the consumer market. Complexity is increasing at each node – as shown in the prior slide. One major way the industry has dealt with this rising complexity is through IP reuse.

Feldhan next observed that derivate designs represent about 60% of the overall design – which make up the 13,000 design starts mentioned earlier (see Figure 4). Note that the lower green bar, which represents high performance SOCs, is growing because companies are trying to reduce their risk with Performance SOCs by developing derivative designs. Also, there is significant growth in the Value and Basic SOC markets on the top. So while first time designs were just under 5,000 (about 4,900) in 2020, reuse designs will reach nearly 8,400 (or 13,300 – 4,900 = 8,400) by 2020. Even in 2016 reuse designs will total 6,800, which will exceed the number of first time designs for Performance SOCs in 2020. From these numbers, one can see the value of reuse to recoup some of SOC investments and take advantage of the existing design from one’s first time efforts.

Figure 4: The value of SOC IP reuse.

Complexity – Trends and Challenges for Reuse

Feldhan shift his attention to the challenges and trends for reuse. As mentioned, complexity is a big issue. To measure complexity, we looked at the number of gates (in kilos) in current designs. For example, in 2015, the average SOC had about 34M gates. By 2020, we predicate that number to escalate to 78M gates. This tremendous increase in the number of gates will only add to the complexity of SOCs. We predict the growth rate to increase by between 15% to 23% per year between 2017 and 2020.

Another way to think about design complexity is to look at it historically (see Figure 5). We decided to measure today’s complexity by comparing it with designs in 2002 (which had a design complexity of “1”). These comparisons were grouped into end applications. As you might expect, the highest complexity parts were in the computer areas, e.g. servers, cloud applications, traditional notebooks and tablets. Communication applications were also high in complexity, e.g., servers, routers, switches and smart phones.

Figure 5: By 2020, computer and communication design complexities will be almost 130 times since 2002.

In 2015, computer and communication SOCs were about 60X times more complex than in 2002. By 2020, these same SOCs will be almost 130 times more complex then what we saw in 2002. These numbers are meant to convey the magnitude of complexity facing chip designers, explained Feldhan Companies are really taking a significant risk pursing future SOC design, which is why IP reuse is so important.

Perhaps not surprisingly, the number of IP blocks in an SOC design is escalating almost at an exponential rate (see Figure 6). The important takeaway here is that fastest growing IP blocks are system block, i.e., not memory or processor functions but all the other types of IP. The “all other” types of IP will grow to over 90 blocks per SOC design. The “other” blocks are can be highly complex since they may not have an established, structured architecture as does memory or processor blocks.

Figure 6: Growth in IP blocks (memory, processor and other system IP) incorporated into a SOCs.

Cryptography and security are among the most popular types of IP blocks incorporated into SOCs – especially in the IOT market (see Figure 7). All kinds of connected devices, from factor floor automation to smartphones and automobiles, will require security. The broad scope of other IP applications shows the complex ecosystem for SOC designs. Also, it illustrates the high cost and complexity of SOC designs per process node as was previously mentioned.

Figure 7: Leading types of IP reuse.


In terms of trends, IP reuse will be predominant in the IOT market. Basic SOCs will be the most popular as they are the least cost sensitive. The availability of third party IP will be one of the ways the IOT chips market will achieve tight time-to-market requirements. This is particularly key for the consumer market. The use of subsystems and mega-blocks IP will enable reuse and allow for derivative designs to be even more cost effective.

From a Performance SOC standpoint, reuse and derivative designs allow companies to recover their high initial cost investment. As already mentioned, cost reduction is a key to low end consumer products but it is also a huge factor in the high performance market. For the Performance SOC market, complexity reduction through reuse and subsystems are ways to minimize the escalating cost.

Although not mentioned, better documentation of design methodologies greatly helps to enable reuse and future modification for other IP.

In summary, here are the key takeaways for why IP reuse is important in today’s SOC designs.

> Without IP reuse, SOCs would struggle to meet time-to-market constraints, cost targets and performance goals.

> Reuse subsystems allow for higher level chip integration and allows for lower IP cost integrations.

> The ability to reuse IP within a company encourages a company culture of increased communications and supports a culture of teamwork and sharing. This allows engineering teams to spend more time on other critical chip issues.

> IP is a proven asset. It doesn’t need a lot of engineering support.

> Simplifying procedures and methodologies will accelerate IP reuse.

In closing, we see a bright future for IP reuse. It will be critical to the success of the SOC market, especially in the IOT and related markets

Q&A: Will M&A Activity Affect Reuse?

Blyler asked the following question at the end of Feldhan’s presentation: Some wonder if the continuing merger and acquisition (M&A) activity in the SOC design and manufacturing market will negatively affect design starts, i.e., will more consolidation in the market result in fewer designs.

Feldhan explained that one line of thought is that will consolidations will lead companies to reduce R&D investment as well as design starts. I don’t think that the available data supports this assumption. The main reason is that costs are escalating on the R&D side.  Here, M&A may help as they have brought companies together which has helped hold R&D down to the 14 to 16%. In markets where you don’t have consolidation, you have duplication of R&D activity which makes the total industry R&D more expensive.

The effects of M&A activities on design starts is less clear. For example, Freescale merged with NXP which soon may become part of Qualcomm. Will Qualcomm still invest in Freescale’s IMAX processor architecture? They may or may not. If not, it may not be a bad thing. Instead of maintaining Freescale’s IMAX product, Qualcomm may decide to create more derivative designs to fit the IMAX functionality into Qualcomm’s own Snapdragon product line. From that standpoint, I think some of the mergers may help the reuse market as some product lines will be consolidated while others will be supported with additional reuse design efforts.

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