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Tag Archives: verification

The UVM Factory Object and Encapsulation or For God’s Sake Don’t Touch that Code!

The often-misunderstood UVM factory object provides a path to modify testcase behavior without the associated doom of touching already released code. by Hamilton Carter, Senior Editor All of us have seen some variation of the following flow chart:   The basic message, “If you can get away without touching it, you might just be OK,” applies as well to design verification ... Read More »

IP Systems Blog Review – Tuesday January 20, 2015

Android assembly programming, Sample and Hold Time for Dummies, near field communications, and the secret origin of the Udacity functional verification course By Hamilton Carter, Senior Editor The Altera SoC FPGA was selected for Audi’s advanced driver assistance system, (ADAS). How to program in assembly on an ARM/Android device. Mentor’s Josh Rensch provides quirky, irreverent advice on how design and ... Read More »

IP Systems Blog Review – Friday January 2, 2014

The holidays aren’t over yet!  Mentor’s Boris Marovic considers the science behind Santa.  Alien technology abounds. Follow an ex-Sparkfun engineer in his travels across Africa spreading robotics. Jama moved into a new headquarters for the new year! Things are a bit slow what with all the mandatory holiday shutdowns.  Here’s some fun holiday reading about the Blocks for the Intel ... Read More »