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Tag Archives: Cadence

EDA Tool Reduces Chip Test Time With Same Die Size

Cadence combines physically-aware scan logic with elastic decompression in new test solution. What does that really mean? By John Blyler, Editorial Director Cadence recently announced the Modus Test Solution suite that the company claims will enable up to 3X reduction in test time and up to 2.6X reduction in compression logic wirelength. This improvement is made possible, in part, by ... Read More »

IP Systems Blog Review – Tuesday April 28, 2015

Big data and verification; reading design specs; all-digital radio; protocols: WiGig and HART; more from the Wilson verification study: FPGAs; the Studebaker plant gets a new lease on life; verification sequence portability; NASA space apps; draw a barn with SystemVerilog constraints; Industrial automation and the IoT; and upcoming events Read More »

IP Systems Blog Review – Tuesday February 24, 2015

Buffer, and ADC design considerations; all about timing specifications; portable stimulus; Star Trek and the IoT; the Wilson Group's functional verification study; RTOS performance; the Silicon Valley age gap; temperature and humidity sensors; requirements management; and the oft-dreaded question "What do you do for a living?" Read More »