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Lunch & Learn – Validate Embedded Software on Real Hardware

Understand the challenges and techniques in validating embedded software on real hardware at Cadence’s FPGA-based prototyping”Lunch & Learn.”

To the readership: I’ll be speaking at the upcoming Cadence “Lunch & Learn.” My topic will be the trends in embedded prototyping of hardware and software systems.  Please consider this event if your doing any ASIC with embedded software prototyping. Cheers — JohnB

 

FPGA-based prototyping is hard to do—or is it?

How long does it take you to bring up your multi-FPGA, or even single-FPGA prototype? Two months, three months, more? If it takes you longer than two
WEEKS, then read on, attend this event, and learn how you can reduce the bring-up time from months to weeks!

In this interactive and hands-on lunch and learn seminar, you will experience
firsthand how 
the new Cadence® Protium™ rapid prototyping platform can make FPGA-based prototyping more productive and easier to use than ever beforeWe will walk you through the
steps to implement a complete SoC design with embedded processor, memory
, and peripherals into a multi-FPGA prototyping system. In
addition, experts will provide
 practical help on how master the challenges in FPGA-based prototyping and how to make your prototyping project a success. 

Date and location 

  • Thursday, May 7, 2015: 10:00am – 1:00pm, San Jose, CA 
  • For other locations, please contact Juergen Jaeger at juergen@cadence.com 

Agenda

Time Session
9:30am Registration
10:00am
Introduction and Overview
10:15am
The Growing Need to Validate Embedded Software on Real Hardware (John Blyler, JB Systems)
10:30am Does FPGA-Based Prototyping Really Have to Be this Difficult?
11:15am Hands-On Demonstration: Step-by-Step Implementation of an Embedded System SoC & Booting LINUX and Running Apps
12:00pm Lunch and Q&A

Attend for your chance to win a JAWBONE MINI JAMBOX!

Space is limited. Register today!  

Register Now

 

 

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