All’s well at TSMC; safety standards impact embedded SW; VIP, buy or build?; software security; debug automation; glow-in-the-dark neurons; and an anniversary in semi-vlogging.
by Hamilton Carter – Senior Editor
10 nm processes at TSMC are good to go! There are some changes that designers will have to work with, like the requirement of color-aware tools and a different spacer technology. Scaling is still holding up though. TSMC has demonstrated a 256 Mb SRAM in the 10 nm technology that is close to a 50% scale down from the 16 nm process. Dr .Cliff Hou and Dr. BJ Woo, both from TSMC, spoke about the technology at the recent TSMC 2015 Technology Symposium.
Mentor’s Colin Walls talks about the impact standards like ISO26262, DO-1786, and IEC 61508 have on embedded applications. Tips are provided on how to select your software IP including the RTOS, and how to streamline your IP to reduce standards-based certification efforts.
Should you buy your VIP or roll your own? The Verification Gentleman weighs in on the debate by reflecting on his recent experiences writing VIP at Infineon.
Synopsys announced that they’ll be adding to Coverity’s security portfolio through their acquisition of Codenomicon.
Cadence’s VP of Engineering for the Advanced Verification Solutions Group, Shlomi Uziel, talks about the ins and outs as well as the ups and downs—abstraction-wise—of SoC debug. This is a great thought provoker for ideas on how you could streamline debug on your next development project.
A fun edge-of-science read: Rambus talks about the possibilities inherent in lenseless sensors and the recent development of ‘…genetically modified harmless viruses to make living nerve cells (neurons) rapidly glow or fluoresce as they fire…’
Altera and TSMC announced that they’ve co-developed under-bump metallization-free (UBM free) technology resulting in thinner chip packages and higher reliability.