High-level synthesis in design and verification, layering UVM constraints, FORTRAN? still?, parallel algorithms, two new (and free!) VIPs from AMIQ; the NVMe SSD standard; and Apple batteries and the IoT
by Hamilton Carter – Senior Editor
Dave Purley begins a new high-level-synthesis blog for Cadence. This entry simply introduces the blog, but Dave hopes to build a platform for engineers to discuss their views on the topic.
Learn how to layer constraints in SystemVerilog as well as emulate multiple inheritance using the mixin design pattern on the Verification Gentleman blog. This interesting post points out the use of design patterns already embedded in UVM and discusses adding another pattern to overcome SV’s single inheritance only model.
Fortran is still alive and evolving! Intel’s Steve Lionel discusses the latest specification Fortran 2015.
Is your embedded application running out of steam in your single processor design? Add more processors! Altera’s Ron Wilson discusses the many options for breaking your algorithm apart into parallelized versions of themselves.
Focusing back on verification, here’s a post that looks to the details, all the details, of using UVM enabled sequences.
Intel details the NVMe standard for solid state drives.
The Apple watch and what it can tell us about challenges facing the IoT, (it’s all about batteries: making them last longer, or using them less).