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IoT Hardware Needs Re-Architecting

Achieving the lowest digital and analog system power on a single IoT chip requires re-architecting and optimization.

By John Blyler, Editorial Director, IoT Embedded Systems

As leading provider of chip design tools, Synopsys has just announced a portfolio of IP specifically optimized to address security, wireless connectivity, energy-efficiency and sensor processing requirements for a wide range of IoT applications.

V1041_IP4IoT_Blyler-Lowman_tmb1_FINAL2To better understand the technical and market challenges addressed by the announcement, please watch my video interview with Ron Lowman, Strategic Marketing Manager at Synopsys.

Luke Collins at the Tech Design Forum provides a broader view on this announcement.

For a more technical explanation as to why re-architecting and optimization were needed for this IoT platform, please read the following interview with Ron Lowman and James Wu, Strategic Marketing Director at Synopsys. – JB

 

Blyler: You’ve listed the key IoT design requirements as connectivity, security, energy efficiency and sensor processing. To meet each of those requirements, Synopsys has made major investments – recently in the connectivity and security area – to expand the company’s portfolio. Equally important has been the integration, re-architecting and optimizing the various IP for IoT designs. How exactly have you re-architected and optimized the IP?

Lowman: We’ve ported all of the SoC IP functionality just mentioned to ultra-low power process nodes, i.e., 55nm and 40nm. Portions of the existing IP had to be re-architected for low power modes, low terminal voltage, low leakage and low cost. Additional power efficiency was obtained by reducing the processor cycle count and frequency. Here are the specifics:

  • USB 1.1 & 2.0 – Re-architected for smaller area, lower power; ported to established nodes (55nm now and 40nm in the future)
  • Data Converters – low power modes; ported to established nodes.
  • Memory Compilers – 0.9V operation, high-density cells.
  • Logic Libraries – Since voltage is a huge contributor to power use, the IP now supports low voltages down to 60% of VddNom. Further, the IP has a thick oxide library to enable lower leakage. It’s important for designers to minimize the amount of power leakage as most applications are “off” for a majority of the time.
  • Non-Volatile Memory – Reprogrammable EEPROM within the SoC helps save costs on external EEPROM. Also, there are no mask adders or processing steps for the NVM.
  • ARC EM- Configurable, extensible, ultra-low power processing cores have reduced cycle count and frequency which improves the efficiency of the work being preformed. This, in turn, reduces the overall power consumption.

Blyler: Does this platform have similar improvements on the analog side?

Lowman: The analog side of our Iot IP platform consists of data converters and USB PHY, all of which has been ported to 55nm and soon 40nm. We applied learning’s from our USB 28nm FemtoPHY offering and back-ported those learning’s to both 40nm and 55nm, i.e., optimizing die size, lowering overall power, etc.

Blyler: How have you handled the connectivity piece – RF and wireless (Bluetooth)?

Lowman: We acquired our Bluetooth (BT) IP a little over two months ago from Silicon Vision. It already supported 55nm down to 1v, which is a key feature for low power.

Wu: A benefit in the low power re-optimizing of IP is that semiconductor-manufacturing suppliers like TSMC and others are coming up with new innovation in existing geometries. One example is TSMC’s Ultra Low Power (ULP) platform at 55nm for which they co-supply voltage from 1.2 to .9v. But those voltages introduce new challenges. Existing USB 1.1 and 2.0 standards are well understood and have been used in industry for more than 15 years. But when your supply voltage drops from 1.2 to .9 v, the device performance is reduced by 70%. We found out that we couldn’t close timing by staying with the existing USB architectures. Instead, we had to create new mechanism to meet the requirements. This is but one example of what we have to deal with and why re-optimization was needed.

Blyler: What did you do to close timing in this example?

Wu: We worked with our ARC processor leaders to understand what was acceptable. Sometimes, the solutions was as simple as inserting a voltage regulator in the device. Then, in the USB data transfer mode, you boost the entire chip back into 1.2v. That is one way. Or you have to inject in different Vt device or faster device type to achieve timing closure. It’s been a really learning process to overcome these challenges to bring out the IoT platform.

Lowman: In addition to low overall power consumption, there is another reason to move to 1.1v or 0.9v. If you have a product that can operate down below 1v, then you can really extend the battery life of a single cell AA battery. Most current solutions at 90nm will require two AA batteries because ICs at the node are already near the batteries end of life of 1.8v. A single cell battery will start at 1.8 volts for the battery but over it’s life will drop to about .9 or 1v before it just stops operating and you need to recharge or just throw it away. Developing solution at the more aggressive processes like 55nm and 40nm can lower costs maintaining the same battery life.

Blyler: Thank you.

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