Much has been written about the recent interplay between electronicdesign- automation (EDA) tool vendors, chip manufacturers, and foundries. Numerous editorials have conjectured about the outcome of this interplay, such as Peggy Aycinena’s “When Will TSMC Buy Cadence?” News items hint at the fundamental shift that’s taking place in the industry. Consider the recent report that the world’s largest pure-play chip foundry, TSMC, has spent over $100 million in the last five years to create its own design blocks and intellectual property (IP). This change suggests that the foundry is moving toward a more ASIC-like business model. Meanwhile, traditional chip companies like Texas Instruments (TI) and STMicroelectronics have announced that they’re getting out of the foundry business for 65 nm and beyond.
Even on the EDA-tool side of the chip equation, major foundries-again, primarily TSMC-are now offering a wealth of design-for-manufacturing (DFM), design-for-yield (DFY), and other EDA-type tools. Naturally, there are justifiable reasons for foundries to offer tools that make use of their vast amounts of proprietary process data. Yet such offerings-when combined with the aforementioned move into the IP space-do beg the following question: Will existing EDA vendors have a market for their tools in the next decade or so?
To answer this question, I decided to focus on the common denominator of intellectual property. Here, I mean IP as it applies to both hard and soft design IP as well as process data IP. With such a common denominator, I decided to talk with industry executives well connected with the IP, EDA, IDM, and foundry markets.
They saw it as an interesting twist that foundries like TSMC are starting to come out with their own intellectual property-in essence, competing with their own partners. This is perhaps understandable, as foundries like TSMC strive to differentiate themselves from commodity wafer providers. Still, foundries that offer IP-are becoming more like ASIC vendors. At some point, they could conceivably sell standard products. They would then become a new generation of chip companies. Although my sources were not sure that it will go that far, other developments certainly suggest a chance for the ASIC business model for smaller-geometry chips.
For example, consider the rise in DFM and DFY tools at 90 nm and below. As designs move into smaller and smaller geometries, the EDA tools have to be more tightly coupled to the process technology. The most efficient way to achieve that goal is to have the foundries that have the manufacturing facility. As noted earlier, however, there will be fewer and fewer fabs at the 45- nm level and below. The few remaining fabs like TSMC will therefore have to deliver very detailed and robust process data to the EDA vendors or provide the tools themselves.
This latter scenario has fired up the imagination of many observers. First, non-commodity foundries offer design blocks and IP. Next, these same foundries start to own the tool chain by offering the greatest DFM-DFY tools for their own processes. Suddenly, the cycle started 15 years ago is complete. Then, the only companies making the EDA tools were the big IDMs like LSI. “At that time,” one of my sources mused, “LSI had the biggest internal CAD group of any other company.” Now, that dubious honor is held by IBM and Intel. “But,” my source added, “I talk to Intel almost every week, and they tell me that they’ve got these directives to use more external tools.” Developing and maintaining internal tools at 65 nm and below is just too expensive-just like building a new fab. Bingo. From IP to tools to fabs.
Where will it end? Will the cycle just repeat itself? It probably won’t, which is why I prefer the analogy of the spiral in which the cycle ends at a new set of end points. My sources believe that those new boundary conditions will be marked by the commercial realization of nano- and quantum-computing. “Maybe in another 10 years or so, all this silicon stuff will just be old news,” one suggested. If the last 20 years are any indication, he’s probably right. In that time period, the semiconductor industry successfully created chips from 10 microns down to 65 nm. One can only guess at what the market landscape will look like at the end of this spiral.
Originally Published in Chip Design magazine