New data shows that the break-even, return on investment (RoI) point continues to fall as custom SoCs compete directly with traditional discrete IC board designs.
By John Blyler, JB Systems
> “Is a single SoC really a viable alternative to board-level implementations? … no matter the process node, there is always a (proportionally) hefty NRE.”
> “Small to medium businesses care much less about the unit cost than in minimizing their NRE cost.”
> “The breakpoints occur where the foundries force small and medium customers to transition from a MPW to a dedicated mask (see Figure).”
> “The real tipping point (for affordable custom SoCs) occurred around 2010 to 2011 when three things happened – decreasing price of silicon, emergence of specific application domains, and a fragmented IoT market… in which large companies have no particular advantage.”
> “So how can OEM’s determine this break-even point? First, they must get a reasonable estimate for the cost of a custom SoC … (following the) Rule of 50”
> “Hardware is the new software.”
> “… (a) carpet machine company moved to a customer ASIC instead of the traditional discrete component board. To their satisfaction, that product has been the only machine that wasn’t cloned.”
For years it’s been acknowledged and even trendy to cast hardware as a mere commodity. In general, software has replaced hardware as the differentiator in the embedded space. Hardware has become a commodity in part due to the benefits offered by Moore’s law in power, performance and price.
But in the semiconductor chip world, Moore’s Law is finally slowing. While transistor density continues to increase, the rate is decelerating. In 1990, transistors doubled every 18 months while today that happens every 24 months. As Andrew Huang notes in a recent IEEE article, “transistor density improvements will slow to a pace of 36 months per generation, and eventually they will reach an effective standstill.”
The slowing of Moore’s Law applies to leading edge geometric nodes, now somewhere near 14nm. But what is often forgotten is that trailing edge, mature nodes are still decreasing in price. For example, 180nm wafer costs continue to decrease by about 5% per year.
What happened to make custom ASICs an affordable implementation strategy for start-ups and small to medium businesses? The answer lies in the falling wafer costs at mature nodes combined with the emergence of application domains that are well suited for these mature technologies and the low volumes in the very fragmented IoT market.
Another converging trend is the staggering economic damage caused by the theft of intellectual property (IP) and the cloning of board-level designs. But here, too, ASIC’s provide a benefit. It is very difficult to reverse engineer a custom ASIC. That’s one reason why Jio Ito, the director of the media lab at MIT, calls hardware the new software. Today’s hardware startups look like yesterday’s software counterparts. That is why the spin-offs coming out of MIT are actually working in hardware rather than software – because of the falling costs of ASICs and the afforded IP protection.
Finally, custom ASICs are a bulwark against the supply chain obsolescence of board-level components. When a supplier decides to stop supplying a particular component, the customer may have to redesign their product board. The end-of-life (EoL) scenario is a significant trigger for many companies when considering a custom SoC.
Want to learn more? Please read the details in the whitepaper: Custom SoCs Compete with Discrete IC Boards