JB Systems Tech Engineering and Media Company
Unique exhibition and trade show levels the playing field for customers and vendors as semiconductor intellectual property (IP) reuse grows beyond EDA tools. Read More »
New Event Focuses on Semiconductor IP Reuse
Featured Stories
Has The Time Come for SOC Embedded FPGAs?
Shrinking technology nodes at lower product costs plus the rise of compute-intensive IOT applications help Menta’s e-FPGA outlook. By John Blyler, IP Systems The following are edited portions of my video interview the Design Automation Conference (DAC) 2016 with Menta’s business development director, Yoan Dupret. – JB John Blyler’s interview with Yoan Dupret from Menta Blyler: You’re technology enables designers to include ... Read More »
One EDA Company Embraces IP in an Extreme Way
Silvaco’s acquisition of IPextreme points to the increasing importance of IP in EDA. Read More »
Specs vs. Implementation; Portable Stimulus; Hardware-Software Differences
Accellera’s Chair, Shishpal Rawat, talks about the expanding Accellera-IEEE relationship, the need for portable stimulus and why SystemJava would be difficult. Read More »
Verifying Virtual Prototypes Key to IOT Success
Yatin Trivedi, DVCon Chair, talks about Internet-of-Things verification issues and differences between standard specifications and implementations efforts. Read More »
Semiconductor Technology Enables Mobile Spectral Imagers
Start-up SCiO prototypes a pocket-sized molecular scanner based on spectral imaging that tells you everything about your food. Read More »
EDA Tool Reduces Chip Test Time With Same Die Size
Cadence combines physically-aware scan logic with elastic decompression in new test solution. What does that really mean? By John Blyler, Editorial Director Cadence recently announced the Modus Test Solution suite that the company claims will enable up to 3X reduction in test time and up to 2.6X reduction in compression logic wirelength. This improvement is made possible, in part, by ... Read More »
The Dangers of Code Cut-Paste Techniques
A common coding practice can lead to product efficiency but also software maintenance nightmares and technical debt. Read More »
Scottish Firm Uses Optimization to Move Beyond EDA to Embedded
Criticalblue’s CEO David Stewart reveals how software driven hardware performance optimization moved them beyond the chip design world. Read More »
Software and Memory Footprint Challenge Traditional EDA
Software running close to the silicon hardware still presents many challenges for designs in terms of memory footprint optimization and security vulnerability. Read More »