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Has The Time Come for SOC Embedded FPGAs?

Shrinking technology nodes at lower product costs plus the rise of compute-intensive IOT applications help Menta’s e-FPGA outlook. By John Blyler, IP Systems The following are edited portions of my video interview the Design Automation Conference (DAC) 2016 with Menta’s business development director, Yoan Dupret. – JB John Blyler’s interview with Yoan Dupret from Menta Blyler: You’re technology enables designers to include ... Read More »

EDA Tool Reduces Chip Test Time With Same Die Size

Cadence combines physically-aware scan logic with elastic decompression in new test solution. What does that really mean? By John Blyler, Editorial Director Cadence recently announced the Modus Test Solution suite that the company claims will enable up to 3X reduction in test time and up to 2.6X reduction in compression logic wirelength. This improvement is made possible, in part, by ... Read More »