Louisville, CO – March 4, 2016 –The 2016 Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative, concluded this week with attendees filling the many presentations, panels, posters, and keynote offered during the intense four-day technical program. With the addition of Europe and India, DVCon now serves more than 2,000 attendees worldwide each year.
Overall attendance, including exhibit-only and technical conference attendees, was 882. Attendance was further enhanced by 295 exhibitor personnel that also had access to the panel sessions and keynote address, for a total of 1,177 participants.
The Award for Best Paper Presentation, as voted by conference attendees, went to Eldon G. Nelson, Intel, for his presentation titled, “Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog.” Second place was awarded to Stan Sokorac, ARM, for his presentation, “SystemVerilog Interface Classes – More Useful Than You Thought,” and third place was awarded to Zhipeng Ye, Honghuang Lin, and Asad Khan, Texas Instruments, for their presentation, “Functional Coverage Collection for Analog Circuits – Enabling Seamless Collaboration Between Design and Verification.”
Top honors for Best Poster went to Lun Li, Durga Rangarajan, Christopher Starr, James Greene, Samsung Austin R&D Center, and Nitin Mhaske, Synopsys for their poster, “Marrying Simulation and Formal Made Easier!” Second place was awarded Krishnan Balakrishnan, Courtney Fricano and Kaushal M. Modi, Analog Devices, Inc. for their poster, “Improving the UVM Register Model: Adding Product Feature Based API for Easier Test Programming,” and third place was awarded to Neil Johnson, XtremeEDA, and Joshua W. Rensch, Superion Technology for their poster, “How Do You Verify Your Verification Components?”
“We congratulate our Best Paper and Best Poster Winners for 2016,” stated Ambar Sarkar, DVCon U.S. Program Chair. “In its 28th year, we are proud that DVCon U.S. has continued to be the must-attend design and verification conference for the practicing engineer. As it has grown and evolved over the years, it continues to offer an unparalleled selection of relevant technical material in the keynote, tutorials, papers, panels and poster sessions.”
“The exhibit floor is also an area where attendees have come to meet with peers and exhibitors to continue their discussions and share information,” continued Yatin Trivedi, DVCon U.S. General Chair. “At Accellera, because of the demand for the information worldwide, we have decided to expand the global reach of DVCon beyond the U.S., India and Europe to also include China in 2017. We want to make sure that the global design and verification engineering community has access to the outstanding technical programs offered by DVCon.”
Highlights of the Week:
Accellera Day opened the conference on Monday. Erwin de Kock, a Principal Engineer at NXP Semiconductors, was recognized during the Accellera-sponsored luncheon as the recipient of the fourth annual Accellera Technical Excellence Award. He is a member of the IP-XACT Working Group.
On Tuesday Dr. Wally Rhines, Chairman and CEO of Mentor Graphics, delivered an engaging keynote that discussed the design verification challenges from the past, present and future to a full ballroom of more than 320 attendees.
The two panels on Wednesday were well-attended and provided some thoughts for further discussion. Audience members were intrigued by the panel on emulation and asked many questions regarding whether or not emulation or static verification, like formal, could replace simulation. The panel on ESL had the audience debating what a higher level of abstraction would look like in a verification flow with embedded software.
The DVCon Steering Committee values all feedback regarding the conference. Attendees have been given a survey and are asked to provide input on how to make DVCon U.S. 2017 even better.
Save the date: DVCon U.S. 2017 will be held February 27 – March 2, 2017 at DoubleTree Hotel in San Jose, California. DVCon India 2016 will be held September 15-16 in Bangalore, India and DVCon Europe 2016 will be held October 19-20 in Munich, Germany.
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors DVCon Europe and DVCon India. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook or @dvcon_us on Twitter or to comment, please use #dvcon_us.
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